Latest UPDATE from BA
Progress update - 20 Feb 2014
1.Following Verisilicon’s tapeout final review meeting it was decided that they need to update the IO and metal according to Analog IO team requirement. VeriSilicon needs additional 36 hours to extract the final specification of GDS and run STA. At the same time FE needs to run POSTSim based on the final Netlist. As this is a 100 million gate design it requires intensive CPU support. VeriSilicon agreed to work over the weekend to maintain our working schedule and are confident that the files will be sent to the factory in 36 hours.
2.We finished the hash board for X1. We will review and send to the factory tomorrow. The board was designed for a maximum of 160A (exceeding the 88A @ 0.85V required).
3.Each X3 module will use 5 hashboards and will have 2 Minion ASICs. This solution was chosen to support the high current (up to 33 Amperes @ 12V) required by the power chips. Another issue which we had to overcome was the fact that the smaller connectors already available on the market were either too big or had too few pins to support a single ASIC hash board 35mm wide. We are in the process of designing 2 different boards for the X3 hashboard: 2 x 160A and 2 x 200A to support extreme overclocking. The final decision of which PCB we will use will be taken after we’ve tested the real silicon.
4.We have finished the control board for X1 & X3 and will send it tomorrow to the factory. 3 months ago we decided against using Raspberry PI or Beagle Bone. RPI proved too unreliable during extensive usage and none of them would satisfy our requirements. We’ve opted instead to design our own board based on ARM chip. This task was equivalent of designing a whole new Raspberry PI and was major design work. We are convinced that our customer will benefit the extra features.
5.We have entrusted AMKOR for packaging the Minion. We had several meetings last week in order to choose the best package and have decided to go with Stiffener FCBGA instead of Lidded FCBGA as previously announced; this package provides better cooling performance and will have extra capacitors on the substrate.
6.We’ve maintained a very busy meetings schedule with VeriSilicon to clarify the PO and packaging.
7.Following the feedback of our case designers we have hold a meeting with the PSU factory and agreed:
a.To shorten the PSU for the X1 with 10mm in order to get closer to our 200x200x70mm case target.
b.To reduce the height of the X3 PSU by 20mm in order to be able put the Ethernet connector in the back of the case.
8.We have increased the heatsink fins thickness to 0.5mm, asked the factory to produce 2 samples (1.8mm spacing and 2mm spacing).
9.We have met with potential resellers but this cannot go on. We receive so many meetings requests and unfortunately we will have no option but to decline them as our management team has more pressing issues to deal with currently; our commitment is with our existing customers and ensuring the sold products are delivered. We will review this process at later stage.
10.Two months ago we have decided to add up extra features for Prospero products and we’re developing them. The project is on schedule and we aim to have a beta version by 1st of May.
11.We have synthesised our FPGA LTC code and it is mining correctly with 4 cores.
12.Our 1st line customer support team are struggling with the volume of messages posted by our customers. We have sent a representative to Philippines for few days for further training. The initial feedback is encouraging, the current procedures are currently under review and we expect improvements soon.
13.The number of the messages on the forum is overwhelming and we are not in the position to address all of it. Despite all of our efforts we’ll only be able to answer only a proportion
14.We have completed the design and manufacture of the banners for the Texax Bitcoin Conference.
http://texasbitcoinconference.com/ . This announcement confirms that we will be present there; Minersource, Our reseller from USA, will represent us.
